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The economics of volume that have governed the PC marketplace for the past 20 years are now sweeping the server scene. Moore's Law-driven advances in microprocessor performance along with market-driven industry standards are greatly advancing the price/performance and capabilities of mainstream server platforms based on the Intel architecture. (For more information on Moore's Law, please see the feature article by Dr. Gordon Moore in Issue #2 of Platform Solutions. Innovation happens faster as more vendors compete to offer better solutions at lower prices. Improved products attract an even larger market. Prices fall, customers get more value per dollar spent, while vendors continuously improve their efficiency, and the cycle repeats. The result?—newer and better products that draw ever-increasing numbers of users and vendors to this dynamic and richly rewarding opportunity.
These standard, high-volume (SHV) servers—enabled by key technology advances in the areas of scalability, availability, manageability and flexibility—are handling the vast array of old and new business computing models and applications that the current era of network-oriented computing and the Internet has created.
Intel's Processor Roadmap for Servers
Intel designs and builds microprocessors specifically for the server market. Intel's processor roadmap for servers promises to deliver building blocks for new generations of SHV servers that will be capable of delivering truly 'mainframe-class' (and beyond) levels of capacity, processing power and availability. Following Moore's Law, new Intel server-focused processors are rolling out on 18-24 month cycles, with raw performance at least doubling every time. Today's Pentium® Pro and Pentium II processors will soon be joined by Intel's newest processor for servers and workstations with a new, server-specific cartridge configuration called Slot 2. In 1999, Intel plans to deliver the Merced™ processor, the first in a series of IA-64™ architecture processors. Intel will continue to deliver robust roadmaps for both 32-bit and 64-bit processors designed to meet an ever-broadening range of business server computing requirements.
Complementing advances in Intel processor capabilities, SHV servers will also feature continued advancements in L2 (second-level) cache speeds and sizes, increased system bus speeds and bandwidths to support increasing numbers of processors, and significantly enhanced I/O capacity and throughput. In addition, advances in memory technology will enable significantly larger and faster main memories to be affordably implemented in SHV servers, up to a theoretical maximum of 64GB of physical memory (the limit of the 36-bit physical addressability of the IA-32 processor family). Collectively, these advances will enable larger SMP (symmetric multiprocessing) server systems. These platforms will remain well balanced, both in terms of I/O vs. processing capacity for a variety of workloads, and in terms of delivered cost per unit of performance.
To Intel, "scalability" means "never being forced to turn away requests for service due to lack of computer system resources." Intel and the SHV server industry are addressing the scalability challenge in two ways. First is the ongoing, rapid improvement of the performance and throughput of the core electronics complex, including Intel processors and chip sets. There are SHV servers on the market today featuring 4-way SMP, and Intel is working with the industry to deliver 8-way-scalable SHV servers, based on standard Intel Architecture processor building blocks. A number of Intel customers are using these scalable building blocks to construct still larger-scale SMP systems designed to handle the largest workloads of the very largest Global 100 companies.. The second way that Intel is addressing scalability needs is through industry-standard, extremely high-performance methods of combining multiple SHV servers together into robust scalability clusters To bring clustering to the SHV server world, Intel co-developed with Compaq* and Microsoft* the Virtual Interface (VI) Architecture specification which defines a standard mechanism for low-latency, high-bandwidth message-passing between interconnected SHV servers and storage devices and other servers in a System Area Network (SAN). The VI Architecture is designed to enable the SHV server industry to deliver high-performance, scalable clustered systems at a fraction of the price of proprietary RISC and mainframe alternatives. In addition, the portability of cluster-aware software based on VI Architecture will allow customers to run their most complex enterprise applications on more affordable, industry standards-based servers, which should reduce both total cost of ownership and initial cost of acquisition and deployment.
With their inherent capabilities for SMP and clustering, SHV servers will exhibit virtually limitless scalability, regardless of the scale of workloads they are made to handle. In the era of the Internet and e-commerce, effectively limitless scalability is an important characteristic of the server infrastructure.
There are several technology initiatives that establish management capabilities for SHV servers and that provide guidelines for making SHV servers fit smoothly into existing IT management infrastructures. The Wired for Management Initiative (WfM) defines a minimum set of management capabilities for servers. These include requirements for instrumentation, remote wake-up, power management, and server reboot capability. Wired for Management takes advantage of existing standards and management technologies such as DMI, SNMP, and ACPI (Advanced Configuration and Power Interface) and provides developers with a much-needed foundation for designing manageability into server platforms. Along with the WfM baseline specification, Intel offers a set of development tools to facilitate deployment of these capabilities. These include the Intel DMI 2.0 Service Provider SDK, the Managed Objects Toolkit, and the DMI SDK for Servers.
Another key aspect of server manageability in support of the WfM initiative is Server Platform Management Hardware. Intel is working with the industry to define a soon to be released specification that defines a common interface and bus protocol for platform management hardware. This specification will support the WfM initiative which already defines the major server management software standards.
Complementing the WfM initiative and related standards, Intel continues to work on enhancing the manageability features of vital server platform elements including processors, power supplies and critical portions of the system infrastructure. The goal is to have a very high yet broadly available, standards-based level of system manageability and as a result the lowest possible TCO delivered with SHV servers based on Intel Architecture.
Server I/O capacity and throughput are crucial to the overall performance and headroom of the server application. Intel has been working through the years to improve server I/O subsystem capacity and throughput. The results of that effort have already been significant. From ISA to EISA to PCI, and on to multiple PCI buses in a single server, Intel provided much of the core technology and enabling silicon products that permitted these improvements. Another example is the Dual Independent Bus (DIB) architecture, first implemented in the Pentium Pro processor and now part of the Pentium II processor, which dramatically improved memory bandwidth performance.
Though the PCI bus has been the workhorse over the past several years, the processor complex has advanced so fast that the need for more I/O capability only continues to grow. When a single PCI bus supports 64-bit data transfers and runs at 66 MHz (the "peaks" allowed under the PCI 2.1 specification), its 528 Mbyte per second peak transfer rate makes it a much more viable building block for latency- and bandwidth-sensitive server I/O subsystems. Intel processors and chipsets for servers will soon provide a standard foundation for realizing the highest levels of PCI-based I/O capabilities. Newer servers based on Intel Architecture will also feature larger numbers and combinations of (32- and 64-bit) PCI buses, as well as more PCI expansion slots than are generally available in today's SHV servers. At the same time, Intel has started to look into 'next-generation' I/O solutions that will take server I/O capabilities well beyond what PCI can offer today.
In addition to providing the core technologies and building blocks for SHV server I/O subsystems, Intel is also actively promoting the Intelligent I/O (I2O®) Architecture, an industry standard for allowing I/O subsystems to operate in an intelligent fashion by offloading a significant portion of I/O tasks onto specialized I/O processors (IOPs). I2O technology delivers improved driver standardization for all device types, and promises to deliver better system-level aggregate throughput for storage and LAN interactions to end users. In the long-term, I2O technology promises to greatly simplify the process of supporting multiple operating systems and their versions, resulting in more rapid delivery of improved I/O subsystems over time. Products using I2O technology are being delivered today by a number of server systems vendors, independent hardware vendors (IHV's) and operating systems vendors (OSV's).
Today, I2O architecture is directly associated with the PCI bus—the message-passing that occurs between the host OS and the IOP is specifically architected for the PCI bus itself. While this is a fine initial approach, it has a long-term limitation in that realistically there can only be a limited number of PCI buses and associated expansion slots in a given server. Intel is actively working within the I2O SIG (special interest group) to incorporate VI Architecture into the next generation (version 2.0) of the I2O specification. The goal is to bring the benefits of standards-based, high-performance, network-attached I/O to the SHV server platform—regardless of the nature of the underlying system-area network interconnect itself.
Today's SHV servers come in all shapes and sizes. Intel believes that it is both possible and desirable to create industry standards for selected server system design elements such that many different types of SHV systems can be configured from standards-based building blocks. A system vendor or systems integrator could configure a very large-scale compute server, for example, with many multiprocessing compute nodes in a cluster, and relatively little I/O capacity. A large-scale data-warehouse platform could be constructed from many processor and I/O subsystem building blocks. The common denominators between all of these configurations are industry-standard building-block modules and standards-based, high-performance clustering interconnects. One example of this trend in SHV servers is the Server System Infrastructure (SSI) initiative which Intel is leading to define the common elements of current and future server infrastructures, and to help the industry develop a common set of specifications around them.
SHV Servers—Destined for Continuous Success in Business Computing
The SHV servers of tomorrow will offer significant advances over the proven workhorse SHV servers of today. With unparalleled processing power through best-in-class 32-bit and revolutionary 64-bit processors, coupled with state-of-the-art RASM (reliability, availability, serviceability, and manageability) features, native clustering capabilities, and significantly enhanced I/O subsystems, future SHV servers will take on business computing tasks that are hardly imaginable today. Thanks to the innovative and cooperative efforts of the entire server industry, customers can look forward to SHV servers that are more powerful, more flexible, more scalable, easier to manage, and easier to integrate into existing and evolving business computing environments.
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* Legal Information © 1998 Intel Corporation
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